The present invention generally relates to a memory test performance in a semiconductor memory device and, more particularly, to a semiconductor memory device for use in a multiple bit parallel test, reducing memory test time.
In recent years, as a semiconductor memory device or memory array is highly advanced in its density and in its accuracy, a test processing time for checking the memory device is increased accordingly, so greatly that operating current is very largely wasted and the redundancy efficiency is lowered. Since the lowered redundant efficiency requires more redundant memory arrays per chip, the cost for manufacturing the semiconductor memory chip is increased. Therefore, in order to reduce the test processing time prolonged, a parallel test technique is generally used in a semiconductor memory device, i.e., for example, a 4-bit group is used to perform the parallel test in a 1 Mega byte memory device; an 8-bit group is used in a 4 Mega byte memory device ; and a 16- or more than 16-bit group is used in a 16 Mega byte memory device.
Generally, it is necessary for a semiconductor memory device to be able to access multiple bits in order to perform the multiple bit parallel test. A known method is to increase the transistors coupled between the bit lines and the I/O lines in number. In this case, the transistors are controlled by only a single column address decoder, the respective gates of the transistors being coupled to output of the column address decoder, more strictly, to column selection lines thereof. That is to say, it is an approach to improve the parallel test performances by increasing the number of the columns which are selected at one time.
FIG. 1 shows schematically a conventional semiconductor memory device for performing the multiple bit parallel test. As illustrated in the drawing, bit lines BL.sub.1 /BL.sub.1 -BL.sub.4 /BL.sub.4 coupled to respective sense amplifiers SA.sub.1 -SA.sub.4 each of which share a plurality of memory cells M with a row decoder 10 in the manner as shown in FIG. 1. Then, the bit lines BL.sub.1 /BL.sub.1 -BL.sub.4 /BL.sub.4 are coupled to each corresponding source of a plurality of gating transistors 20 of which drains are coupled to the I/O lines I/O.sub.1 /I/O.sub.1 -I/O.sub.4 /I/O.sub.4 and of which gates are commonly coupled to the output of the column decoder 30. The column address decoder 30, receiving column address signals XC.sub.AA, XC.sub.AB provided from a column address buffer (not shown) and receiving a parallel test signal FTE, generates its output to the gates of the gating transistors 20.
However, when a great number of the bit lines are coupled to the output of one column decoder 30 as illustrated in FIG. 1 and, accordingly, the number of columns selected at one time is increased, there arise undesirable problems which are described hereinbelow.
First of all, when implementing a column redundancy operation, which is a technique of replacing a normal column having a defective memory cell by a redundant column in a semiconductor memory device, the output of the single column decoder 30 is the same as that of the columns required for the redundant column. Therefore, when the number of the bits which are accessed at one time during a parallel test mode is increased, the required number of the redundant columns per chip is undesirably enlarged. For this reason, the number of the redundant columns, which is based on the probability of replacing the defective memory cells, is decreased and, at the same time, the efficiency of the memory device is curtailed.
Secondly, if a plurality of the bit lines (or columns) are coupled to the output of the single column decoder 30 so as to access the bit lines BL.sub.1 /BL.sub.1 -BL.sub.4 /BL.sub.4 in the conventional manner of FIG. 1, the I/O lines are coupled at the same time to the bit lines and, therefore, the current is conducted from the I/O lines, which are pre-charged or pulled-up to the bit lines. The current is increased in proportion with to the increased number of the columns. When operated in a normal mode so as to perform the parallel test, the semiconductor memory device consumes a great power relatively. Therefore, the current conducted from the pre-charged I/O lines to the bit lines is reduced, causing a low operating current.